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  1. product profile 1.1 general description the bld6g21l-50 and BLD6G21LS-50 incorporate a fully integrated doherty solution using nxp?s state of the art gen6 ldmos technology. this device is perfectly suited for td-scdma base station applications at frequ encies from 2010 mhz to 2025 mhz. the main and peak device, input splitter and output combiner are integrated in a single package. this package consists of one gate and drain lead and two extra leads of which one is used for biasing the peak amplifier a nd the other is not conn ected. it only requires the proper input/output match and bias sett ing as with a normal class-ab transistor. [1] test signal: 6-carrier td-scdma; par = 10.8 db at 0.01 % probability on ccdf. [2] i dq = 170 ma (main); v gs(amp)peak = 0 v. 1.2 features and benefits ? typical td-scdma performance at frequencies from 2010 mhz to 2025 mhz: ? average output power = 8 w ? power gain = 14.5 db ? efficiency = 43 % ? fully optimized integrated doherty concept: ? integrated asymmetrical power splitter at input ? integrated power combiner ? peak biasing down to 0 v ? low junction temperature ? high efficiency ? 100 % peak power tested for guaran teed output power capability bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mh z fully integrated doherty transistor rev. 2 ? 17 august 2010 product data sheet table 1. typical performance rf performance at t h = 25 c. mode of operation f v ds p l(av) g p d acpr p l(3db) (mhz) (v) (w) (db) (%) (dbc) (w) td-scdma [1] [2] 2010 to 2025 28 8 14.5 43 ? 24 53 caution this device is sensitive to electrostatic di scharge (esd). therefore care should be taken during transport and handling.
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 2 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor ? integrated esd protection ? good pair match (main and peak on the same chip) ? independent control of main and peak bias ? internally matched for ease of use ? excellent ruggedness ? compliant to directive 2002/ 95/ec, regarding restriction of hazardous substances (rohs) 1.3 applications ? high efficiency rf power amplifiers with digital pre-distortion for td-scdma multi carrier applications in the 2010 mhz to 2025 mhz range. 2. pinning information [1] connected to flange. 3. ordering information table 2. pinning pin description simplified outline graphic symbol bld6g21l-50 (sot1130a) 1drain 2 gate + bias main 3source [1] 4n.c. 5 bias peak BLD6G21LS-50 (sot1130b) 1drain 2 gate + bias main 3source [1] 4n.c. 5 bias peak 1 2 5 3 4 1 3 5 2 001aak92 0 1 3 5 2 4 1 3 5 2 001aak92 0 table 3. ordering information type number package name description version bld6g21l-50 - flanged ceramic package; 2 mounting holes; 4 leads sot1130a BLD6G21LS-50 - earless flanged ceramic package; 4 leads sot1130b
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 3 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 4. block diagram 5. limiting values 6. thermal characteristics [1] when operated with a 6-carrier td-scdma modulated si gnal with par = 10.8 db at 0.01 % probability on ccdf. 7. characteristics fig 1. block diagram of bld6g21l-50 and BLD6G21LS-50 001aak932 rf-output/v ds rf-input/bias main 2 5 1 bias peak 90 main amplifier peak amplifier 90 table 4. limiting values in accordance with the absolute maximum rating system (iec 60134). valid for both main and peak device. symbol parameter conditions min max unit v ds drain-source voltage - 65 v v gs(amp)main main amplifier gate-source voltage ? 0.5 +13 v v gs(amp)peak peak amplifier gate-source voltage ? 0.5 +13 v i d drain current - 10.2 a t stg storage temperature ? 65 +150 c t j junction temperature - 200 c table 5. thermal characteristics symbol parameter conditions typ unit r th(j-case) thermal resistance from junction to case t case =80 c; p l =8w [1] 2.1 k/w table 6. characteristics valid for both main and peak device. symbol parameter conditions min typ max unit v (br)dss drain-source breakdown voltage v gs =0v; i d =0.62ma 65 - - v v gs(th) gate-source threshold voltage v ds =10v; i d = 31 ma 1.4 1.8 2.4 v v gsq gate-source quiescent voltage v ds =28v; i d = 170 ma 1.55 2.05 2.55 v i dss drain leakage current v gs =0v; v ds =28v --1.4 a i dsx drain cut-off current v gs =v gs(th) +3.75 v; v ds =10v 4.95 5.5 - a
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 4 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 8. application information 8.1 ruggedness in doherty operation the bld6g21l-50 and BLD6G21LS-50 are capable of withstanding a load mismatch corresponding to vswr = 10 : 1 through all phases under the following conditions: v ds =28v; i dq =170ma; p l = 8 w (td-scdma); f = 2017.5 mhz. 8.2 impedance information i gss gate leakage current v gs =11v; v ds = 0 v - - 140 na g fs forward transconductance v ds =10v; i d = 1.55 a 1.4 2.2 - s r ds(on) drain-source on-state resistance v gs =v gs(th) +3.75 v; i d =1.085a - 0.52 0.736 table 6. characteristics ?continued valid for both main and peak device. symbol parameter conditions min typ max unit table 7. application information mode of operation: 6-carrier td-scdma; par 10.8 db at 0.01 % probability on ccdf; f = 2017.5 mhz; rf performance at v ds = 28 v; i dq = 170 ma; v gs(amp)peak =0v; t case = 25 c; unless otherwise specified; in a production circuit. symbol parameter conditions min typ max unit p l(av) average output power - 8 - w g p power gain p l(av) = 8 w 13 14.5 - db d drain efficiency p l(av) = 8 w 39 43 - % par o output peak-to-average ratio p l(av) = 8 w - 9.4 - db rl in input return loss p l(av) = 8 w 8 23 - db acpr adjacent channel power ratio p l(av) = 8 w - ? 24 ? 20 dbc table 8. application information mode of operation: pulsed cw; = 10 %; t p = 100 s; rf performance at v ds = 28 v; i dq = 170 ma; v gs(amp)peak =0v; t case = 25 c; unless otherwise specified; in a production circuit. symbol parameter conditions min typ max unit p l(3db) output power at 3 db gain compression 46 53 - w table 9. typical impedance measured load pull data; typical values unless otherwise specified. f z s z l mhz 1995 3.5 ? 12.3j 6.7 ? 6.1j 2010 3.6 ? 12.7j 6.7 ? 6.1j 2017.5 3.6 ? 12.7j 6.7 ? 5.7j 2025 3.7 ? 12.7j 6.4 ? 5.2j 2040 4.0 ? 12.9j 5.7 ? 4.8j
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 5 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 8.3 performance curves performance curves are measured in a bld6g21l-50 application circuit. 8.3.1 cw pulsed fig 2. definition of transistor impedance 001aaf05 9 drain z l z s gate v ds =28v; i dq = 170 ma (main); t case =25 c; f = 2017.5 mhz; =10%; t p = 100 s on 1 ms period. (1) v gs(amp)peak = 0 v (2) v gs(amp)peak = 0.2 v (3) v gs(amp)peak = 0.4 v (4) v gs(amp)peak = 0.5 v (5) v gs(amp)peak = 0.6 v (6) v gs(amp)peak = 0.8 v v ds =28v; i dq = 170 ma (main); t case =25 c; f = 2017.5 mhz; =10%; t p = 100 s on 1 ms period. (1) v gs(amp)peak = 0 v (2) v gs(amp)peak = 0.2 v (3) v gs(amp)peak = 0.4 v (4) v gs(amp)peak = 0.5 v (5) v gs(amp)peak = 0.6 v (6) v gs(amp)peak = 0.8 v fig 3. power gain as a function of load power; typical values fig 4. drain efficiency as a function of load power; typical values p l (dbm) 30 50 45 35 40 001aam428 13 15 17 g p (db) 11 (1) (2) (3) (4) (5) (6) p l (dbm) 30 50 45 35 40 001aam429 20 40 60 d (%) 0 (6) (5) (4) (3) (2) (1)
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 6 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor v ds =28v; i dq = 170 ma (main); t case =25 c; v gs(amp)peak =0 v; =10%; t p = 100 s on 1 ms period. (1) f = 2010 mhz (2) f = 2018 mhz (3) f = 2025 mhz v ds =28v; i dq = 170 ma (main); t case =25 c; v gs(amp)peak =0 v; =10%; t p =100 s on 1 ms period. (1) f = 2010 mhz (2) f = 2018 mhz (3) f = 2025 mhz fig 5. power gain as a function of load power; typical values fig 6. drain efficiency as a function of load power; typical values p l (dbm) 30 48 42 36 001aam430 12 14 16 g p (db) 10 (3) (2) (1) p l (dbm) 30 50 45 35 40 001aam431 20 40 60 d (%) 0 (1) (2) (3) v ds =28v; i dq = 170 ma; v gs(amp)peak =0v; t case =25 c; =10%; t p =100 s on 1 ms period. (1) f = 2010 mhz (2) f = 2018 mhz (3) f = 2025 mhz fig 7. input return loss as a function of load power; typical values 001aam432 p l (dbm) 30 48 42 36 20 30 10 40 50 rl in (db) 0 (1) (2) (3)
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 7 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 8.3.2 td-scdma v ds =28v; i dq = 170 ma (main); t case =25 c; f = 2017.5 mhz; 6-carrier td-scdma; par = 10.8 db at 0.01 % probability on ccdf. (1) v gs(amp)peak = 0 v (2) v gs(amp)peak = 0.2 v (3) v gs(amp)peak = 0.4 v (4) v gs(amp)peak = 0.5 v (5) v gs(amp)peak = 0.6 v (6) v gs(amp)peak = 0.8 v v ds =28v; i dq = 170 ma (main); t case =25 c; f = 2017.5 mhz; 6-carrier td-scdma; par = 10.8 db at 0.01 % probability on ccdf. (1) v gs(amp)peak = 0 v (2) v gs(amp)peak = 0.2 v (3) v gs(amp)peak = 0.4 v (4) v gs(amp)peak = 0.5 v (5) v gs(amp)peak = 0.6 v (6) v gs(amp)peak = 0.8 v fig 8. power gain as a function of average load power; typical values fig 9. drain efficiency as a function of average load power; typical values p l(av) (dbm) 22 46 38 30 001aam433 13 15 17 g p (db) 11 (1) (2) (3) (4) (5) (6) p l(av) (dbm) 22 46 38 30 001aam434 16 32 48 d (%) 0 (6) (5) (4) (3) (2) (1)
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 8 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor v ds =28v; i dq = 170 ma; p l(av) = 8 w; t case =25 c; f = 2017.5 mhz; 6-carrier td-scdma; par = 10.8 db at 0.01 % probability on ccdf. fig 10. power gain and drain efficiency as function of peak amplifier gate-source voltage; typical values v gs(amp)peak (v) 0 0.8 0.6 0.2 0.4 001aam435 15 14.5 15.5 16 d (%) 14 40 43 37 39 38 42 41 g p (db) g p d v ds =28v; i dq = 170 ma (main); t case =25 c; v gs(amp)peak = 0 v; 6-carrier td-scdma; par = 10.8 db at 0.01 % probability on ccdf. (1) f = 2010 mhz (2) f = 2018 mhz (3) f = 2025 mhz v ds =28v; i dq = 170 ma (main); t case =25 c; v gs(amp)peak = 0 v; 6-carrier td-scdma; par = 10.8 db at 0.01 % probability on ccdf. (1) f = 2010 mhz (2) f = 2018 mhz (3) f = 2025 mhz fig 11. power gain as a function of average load power; typical values fig 12. drain efficiency as a function of average load power; typical values p l(av) (dbm) 22 42 38 30 34 26 001aam436 12 14 16 g p (db) 10 (3) (2) (1) p l(av) (dbm) 18 42 34 26 001aam437 16 32 48 d (%) 0 (3) (2) (1)
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 9 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 9. test information [1] american technical ce ramics type 100b or capacitor of same quality. the striplines are on a double copper-clad gold pl ated rogers 4350b printed-circuit board (pcb) with r = 3.5 and thickness = 0.76 mm. see table 10 for list of components. fig 13. component layout table 10. list of components see figure 13 for component layout. component description value dimensions c1, c3, c5, c18 multilayer ce ramic chip capacitor 9.1 pf [1] c2, c4, c12, c15 multilayer ceramic chip capacitor 100 nf c6 electrolytic capacitor 470 f; 63 v c7, c8 multilayer ceramic chip capacitor 10 f c9, c10 multilayer ceramic chip capacitor 1.5 pf [1] c11, c13, c14, c16 multilayer ceramic chip capacitor 8.2 pf [1] c17 multilayer ceramic chip capacitor 1.2 pf [1] c19, c20 multilayer cerami c chip capacitor 0.7 pf [1] c21 multilayer ceramic chip capacitor 1.2 pf [1] l1, l2 copper wire - diameter = 0.8 mm; length = 8 mm r1 smd resistor 3.6 1206 r2 smd resistor 33 1206 c1 c19 c20 r2 l1 c9 c10 c7 c8 l2 c14 c15 c16 c11 c12 c13 c6 v dd c2 c3 r1 c21 c4 c5 c18 c17 v gs(amp)main v gs(amp)peak bld6g21-50-v2 input bld6g21-50-v2 output 001aak94 4
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 10 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 10. package outline fig 14. package outline sot1130a references outline version european projection issue date iec jedec jeita sot1130a sot1130a_po 09-10-12 10-02-02 unit (1) mm max nom min 4.65 3.76 1.14 0.89 0.18 0.10 9.65 9.40 9.65 9.40 9.65 9.40 1.14 0.89 17.12 16.10 3.30 2.92 9.91 9.65 0.25 a dimensions f langed ceramic package; 2 mounting holes; 4 leads sot1130 a bb 1 5.26 5.00 cdd 1 ee 1 9.65 9.40 fhl 3.00 2.69 pq (2) 1.70 1.45 q 15.24 u 1 20.45 20.19 u 2 w 1 0.51 inches max nom min 0.183 0.148 0.045 0.035 0.007 0.004 0.38 0.37 0.38 0.37 0.38 0.37 0.045 0.035 0.674 0.634 0.130 0.115 0.39 0.38 0.01 0.207 0.197 0.38 0.37 0.118 0.106 0.067 0.057 0.6 0.805 0.795 0.02 w 2 0 5 10 mm scale d a f l d 1 b c a q c w 2 a w 1 b u 1 u 2 b 1 h b p 42 1 5 3 e 1 q e c note 1. millimeter dimensions are derived from the original inch dimensions. 2. dimension is measured 0.030 inch (0.76 mm) from the body.
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 11 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor fig 15. package outline sot1130b references outline version european projection issue date iec jedec jeita sot1130b sot1130b_po 09-10-12 09-12-14 unit (1) mm max nom min 4.65 3.76 1.14 0.89 0.18 0.10 9.65 9.40 9.65 9.40 9.65 9.40 1.14 0.89 17.12 16.10 9.91 9.65 0.51 a dimensions note 1. millimeter dimensions are derived from the original inch dimensions. 2. dimension is measured 0.030 inch (0.76 mm) from the body. e arless flanged ceramic package; 4 leads sot1130 b bb 1 5.26 5.00 cdd 1 e 5.66 5.41 64 62 z 1 e 1 9.65 9.40 fhl 3.00 2.69 q 1.70 1.45 u 1 9.91 9.65 u 2 w 2 3.05 2.79 inches max nom min 0.183 0.148 0.045 0.035 0.007 0.004 0.38 0.37 0.38 0.37 0.38 0.37 0.045 0.035 0.674 0.634 0.39 0.38 0.02 0.207 0.197 0.223 0.213 64 62 0.38 0.37 0.118 0.106 0.069 0.059 0.39 0.38 0.120 0.110 z 0 5 10 mm scale a d f d 1 l d e q e 1 c u 2 3 u 1 z 1 z h b b 1 d w 2 1 5 42
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 12 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 11. abbreviations 12. revision history table 11. abbreviations acronym description ccdf complementary cumulative distribution function cw continuous wave ldmos laterally diffused metal-oxide semiconductor par peak-to-average power ratio rf radio frequency smd surface mounted device td-scdma time division-synchronous code division multiple access vswr voltage standing-wave ratio table 12. revision history document id release date data sheet status change notice supersedes bld6g21l-50_BLD6G21LS-50 v.2 201008 17 product data sheet - bld6g21l-50_ BLD6G21LS-50 v.1 modifications: ? figure 1 on page 3 : some corrections have been made. ? table 5 on page 3 : the typical value of r th(j-case) has been changed. ? table 6 on page 3 : the values of i dsx have been changed. ? table 7 on page 4 : several values have been changed or added. ? table 8 on page 4 : table has been added. ? section 8.3 on page 5 : figures have been updated. bld6g21l-50_BLD6G21LS-50 v.1 20091028 objective data sheet - -
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 13 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 13.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 13.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interrupt ion, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification.
bld6g21l-50_BLD6G21LS-50 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights r eserved. product data sheet rev. 2 ? 17 august 2010 14 of 15 nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive s pecifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 13.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 14. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors bld6g21l-50; BLD6G21LS-50 td-scdma 2010 mhz to 2025 mhz fully integrated doherty transistor ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 17 august 2010 document identifier: bl d6g21l-50_BLD6G21LS-50 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15. contents 1 product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 general description . . . . . . . . . . . . . . . . . . . . . 1 1.2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 1.3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 pinning information . . . . . . . . . . . . . . . . . . . . . . 2 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 thermal characteristics . . . . . . . . . . . . . . . . . . 3 7 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 application information. . . . . . . . . . . . . . . . . . . 4 8.1 ruggedness in doherty operation . . . . . . . . . . 4 8.2 impedance information . . . . . . . . . . . . . . . . . . . 4 8.3 performance curves . . . . . . . . . . . . . . . . . . . . . 5 8.3.1 cw pulsed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8.3.2 td-scdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 9 test information . . . . . . . . . . . . . . . . . . . . . . . . . 9 10 package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 13 legal information. . . . . . . . . . . . . . . . . . . . . . . 13 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 13.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 13.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 14 contact information. . . . . . . . . . . . . . . . . . . . . 14 15 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15


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